(China (Mainland))
Product Summary
The XC9572XL-10TQG100C is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communications communications and computing systems. It is comprised of four 54V18 Function Blocks, providing 1,600 usable gates with propagation delays of 5 ns.
Parametrics
XC9572XL-10TQG100C absolute maximum ratings: (1)VCC, Supply voltage relative to GND: –0.5 to 4.0 V; (2)VIN, Input voltage relative to GND(1): –0.5 to 5.5 V; (3)VTS, Voltage applied to 3-state output: –0.5 to 5.5 V; (4)TSTG, Storage temperature (ambient): –65 to +150 ℃; (5)TJ, Junction temperature: +150 ℃.
Features
XC9572XL-10TQG100C features: (1)5 ns pin-to-pin logic delays; (2)System frequency up to 178 MHz; (3)72 macrocells with 1,600 usable gates; (4)Available in small footprint packages:44-pin PLCC (34 user I/O pins),44-pin VQFP (34 user I/O pins),48-pin CSP (38 user I/O pins),64-pin VQFP (52 user I/O pins),100-pin TQFP (72 user I/O pins),Pb-free available for all packages; (5)Optimized for high-performance 3.3V systems:Low power operation, 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals,3.3V or 2.5V output capability, Advanced 0.35 micron feature size CMOS Fast FLASH technology; (6)In-system programmable; (7)Superior pin-locking and routability with Fast CONNECT II switch matrix; (8)Extra wide 54-input Function Blocks; (9)Up to 90 product-terms per macrocell with individual product-term allocation; (10)Local clock inversion with three global and one product-term clocks; (11)Individual output enable per output pin; (12)Input hysteresis on all user and boundary-scan pin inputs; (13)Bus-hold circuitry on all user pin inputs; (14)Full IEEE Standard 1149.1 boundary-scan (JTAG) ; (15)Fast concurrent programming; (16)Slew rate control on individual outputs; (17)Enhanced data security features; (18)Excellent quality and reliability.
Diagrams
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IC CPLD 1.6K 72MCELL 100-TQFP |
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