EPM3032ATC44-10N

Product Summary

The EPM3032ATC44-10N is a low-cost, high-performance EEPROM based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EPM3032ATC44-10N operates with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. The EPM3032ATC44-10N contains 32 to 512 macrocells, combined into groups of 16 macrocells called logic array blocks (LABs). The EPM3032ATC44-10N is supported by Altera development systems, which are integrated packages that offer schematic, text-including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)-and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming.

Parametrics

EPM3032ATC44-10N absolute maximum ratings: (1)Supply voltage:–0.5V to 4.6V; (2)DC input voltage:–2.0V to 5.75V; (3)DC output current, per pin:–25mA to 25mA; (4)Storage temperature:–65℃ to 150℃; (5)Ambient temperature:–65℃ to 135℃; (6)Junction temperature:135℃.

Features

EPM3032ATC44-10N features: (1)Enhanced ISP algorithm for faster programming; (2)ISP_Done bit to ensure complete programming; (3)Pull-up resistor on I/O pins during in–system programming; (4)High–density PLDs ranging from 600 to 10,000 usable gates ; (5)4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz; (6)Hot–socketing support; (7)Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance; (8)Industrial temperature range; (9)PCI compatible; (10)Bus–friendly architecture including programmable slew–rate control; (11)Open–drain output option; (12)Programmable macrocell flipflops with individual clear, preset, ; (13)clock, and clock enable controls; (14)Programmable power–saving mode for a power reduction of over 50% in each macrocell; (15)Configurable expander product–term distribution, allowing up to 32 product terms per macrocell.

Diagrams