(China (Mainland))
Product Summary
The EP2C5Q208C8N Altera Cyclone II FPGA extends the low-cost FPGA density range to 68,416 logic elements (LEs) and provide up to 622 usable I/O pins and up to 1.1 Mbits of embedded memory. The EP2C5Q208C8N Cyclone II FPGA is manufactured on 300-mm wafers using TSMCs 90-nm low-k dielectric process to ensure rapid availability and low cost. By minimizing silicon area, the device can support complex digital systems on a single chip at a cost that rivals that of ASICs. The low cost and optimized feature set of the EP2C5Q208C8N make it ideal solutions for a wide array of automotive, consumer, communications, video processing, test and measurement, and other end-market solutions.
Parametrics
EP2C5Q208C8N absolute maximum ratings: (1)VCCINT, Supply voltage With respect to ground: –0.5 to 1.8 V; (2)VCCIO, Output supply voltage: –0.5 to 4.6 V; (3)VCCA_PLL [1..4], PLL supply voltage: –0.5 to 1.8 V; (4)VIN, DC input voltage: –0.5 to 4.6 V; (5)IOUT, DC output current, per pin: –25 to 40 mA; (6)TSTG, Storage temperature No bias: –65 to 150 ℃ ; (7)TJ, Junction temperature BGA packages under bias: 125 ℃ max.
Features
EP2C5Q208C8N features: (1)High-density architecture with 4,608 to 68,416 LEs; (2)Embedded multipliers: Up to 150 18- × 18-bit multipliers are each configurable as two independent 9- × 9-bit multipliers with up to 250-MHz performance; Optional input and output registers; (3)133-MHz PCI-X 1.0 specification compatibility; (4)High-speed external memory support, including DDR, DDR2, and SDR SDRAM, and QDRII SRAM supported by drop in Altera IP MegaCore functions for ease of use; (5)Three dedicated registers per I/O element (IOE): one input register, one output register, and one output-enable register; (6)Programmable bus-hold feature; (7)Programmable output drive strength feature; (8)Programmable delays from the pin to the IOE or logic array; (9)I/O bank grouping for unique VCCIO and/or VREF bank settings.
Diagrams
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IC CYCLONE II FPGA 5K 208-PQFP |
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